The invention relates to electronic devices, and, more particularly, to integrated circuit thermal dissipation structures and methods of fabrication.
The continual demand for enhanced transistor and integrated circuit performance has resulted in downsizing transistor dimensions and increasing operating power densities. This aggravates heat dissipation problems, and for bipolar transistors the threat of secondary breakdown due to hot spots developing limits use of the transistor to the safe operating area (typically defined on a two-dimensional collector voltage-collector current graph). Of course, the safe operating area depends upon thermal design: the transistor junctions generate heat during operation, and the semiconductor material plus packaging materials conduct this heat to the ambient or heat sink. The ratio of the rise in junction temperature to the wattage being dissipated is termed the thermal resistance (thermal impedance) and typical values are 20.degree. C./W for a silicon integrated circuit in a 140-pin plastic quad flatpack; 150.degree. C./W for a silicon integrated circuit in an 8-pin small outline plastic package; and 10.degree. C./W for a 10 W gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) in a monolithic microwave integrated circuit (MMIC). The thermal resistance scales with the chip area, so accurate comparisons would require comparable size chips. FIG. 1 illustrates in cross sectional elevation view a portion of MMIC 100 showing air bridge 102 connecting two source regions of MESFET 104 through a via to ground plane 106 plus microstrip transmission line 108 and wire bonding 110 to lead 122 on alumina substrate 120 which may connect to a coaxial cable. Note that the ground plane typically abuts a heat sink, and that the GaAs die for MMIC 100 is about 100 .mu.m thick. The high thermal resistance for GaAs-based HBTs and MESFETs in part reflects the fact that silicon has three times the thermal conductivity of GaAs.
Heat dissipation limitations for GaAs-based HBTs remain a problem for MMICs and, in effect, require devices be spread out over a large area in order to lower the thermal resistance. This limits integration density.
Flip-chip bonding for silicon integrated circuits allows for a higher density of interconnections than with traditional wire bonding and tape automated bonding (TAB). In flip-chip bonding, solder bumps on the bonding pads on the frontside of a die are aligned with solder-wettable metallization on the carrier substrate, and a solder reflow forms all of the solder bonds simultaneously. For example, Pickering et al., 8 J.Vac.Sci.Tech.A 1503 (1990) discusses the reflow bonding process. In contrast to wire bonding, the flip-chip bond pads may be located anywhere on the frontside of a die and thus simplify integrated circuit layout.
Wong et al, Flip Chip Manufacturing Technology for GaAs MMIC, GaAs Mantech Conference Proceedings 240 (1993), apply flip-chip as a replacement for wirebonding of GaAs MMICs and thereby also facilitate automated hybrid module assembly of MMICs on a single substrate. In particular, Wong et al. follow standard MMIC manufacturing (e.g., patterned ion implantation, ohmic and gate metallization, microstrip and ground plane metallization, and air bridges) but omit wafer thinning and form silver bumps wherever grounding, input/output, and thermal dissipation are needed. The bumps are 75 .mu.m tall and 150 .mu.m diameter, and thermal bumps also cover the top of MESFET source air bridges to remove heat. FIG. 2 (not to scale) shows flip-chip MMIC 200 aligned with insulating substrate 220 and having silver bumps bonding the MMIC die to the substrate, including bump 210 bonding input/output pad 212 to substrate lead 222 and thermal bump 211 providing heat flow from air bridge 202 connected to the source of MESFET 204. The tops of the various bumps (210, 211, and others not shown) have different heights from the surface of the GaAs substrate due to their different bottom heigths, and substrate 220 must be pressed down (and deform) on the bumps to make contact with all of the different bumps.
However, this MMIC flip-chip approach has the problems of requiring a substrate with patterned input/output pads and lines plus thermal dissipation areas and alignment of the MMIC with the substrate. Note that the usual silicon integrated circuit flip-chip approach achieves alignment by reflowing solder bumps; this will not apply to the flip-chip of FIG. 2 due to the high melting point and lack of malleability of the silver bumps.